Electronic communication networks, and devices which utilize them, have become commonplace both in industry and in home environments. Once the sole province of laboratory grade computing equipment, networks interfaces are now found in a broad spectrum of everyday devices including personal computers, children's handheld games, in-the-field data acquisition equipment, portable music players, and more.
To communicate on a network, a device requires an interface that can translate and navigate the specific signals and protocols of that network. As such interfaces have become more prevalent, manufacturers have created increasingly integrated solutions. In some cases, interfaces that once required entire dedicated printed circuit boards full of components are now often available as a single component or “chip”, and even as subsections of larger chips.
Such chips benefit from the well-known economies of scale in the semiconductor industry, yielding dramatic reductions of cost and physical space necessary to add network interfaces to any given device or product. As just one example, to implement an “Ethernet” interface once required parts costing many dollars and perhaps ten square inches of printed circuit board space. As of this writing, that same Ethernet interface is widely available as a standalone integrated circuit (IC) that consumes only a fraction of a square inch at a fraction of the cost. Indeed, if the interface circuitry is included in another integrated circuit already in the system, it is possible to include network support with essentially zero additional overhead.
As with other aspects of the electronics industry, networks continue to advance and improve. The most obvious improvement is data rate: the amount of data that can be transferred over the network per unit time. Whereas a few hundred kilobits per second was considered state of the art just a few years ago, today single-chip interfaces are commonly available that support tens of gigabits per second. Meanwhile, the cost of the interface IC—and thus the expense of including network connectivity—has remained relatively constant. As there is essentially no cost penalty (and significant engineering and marketing advantages) for supporting the fastest and latest networks, most devices simply incorporate the latest generation of network interface IC's with every update and revision.
In most devices, and particularly lower cost products, available network bandwidth now far exceeds the capacity of the host electronics. The microprocessor or other host circuitry cannot keep up with a real-time network data rate of 100 megabits per second (Mbps), 1000 Mbps, and more (analogous to 10-100 megabytes per second). Microcontroller and microprocessor data buses often cannot support such data rates, and the processing cores and other computational components could not do useful work at those rates even if the data could be brought on and off chip. So while the network interface IC may be able to accommodate modern network data rates, its host interface is slowed by the limitations of the host electronics.
Importantly, this throughput limitation is not a problem for those devices needing just a single network connection (or “port”) to connect to a single network. The interface IC sits between the network medium (cable, fiber, etc.) and the host device electronics (microprocessor or other circuitry), translating between the faster network signals on one side and the slower host circuitry on the other. In a single-port device, the host circuitry is the endpoint—the ultimate consumer of the network data—so any limitations it imposes on network interface IC throughput have no ripple effect beyond the device itself. The device's designers select host circuitry based on the intended functionality; more host circuitry speed if the overall device is intended to “do more”, and less speed if less work is required. As long as the network interface IC can transfer data to and from the network at the speeds required by the host circuitry, then the effective network speed—and the network interface IC—is “fast enough.”
In a single port device, then, the choice of host circuitry is driven by the task the device is meant to perform, and not by the peak throughput of the network to which the device will be connected. A device meant to perform a relatively simple or infrequent task can use very simple, very inexpensive host circuitry with its network interface IC. A device intended to do more complex, or more frequent work might incorporate faster and more expensive host circuitry with the same network interface IC. The throughput of the single network port and the network interface IC behind it is automatically and naturally determined by the needs and capabilities of the host circuitry using the network data.
This tidy relationship breaks down, however, when multiple network ports are involved. Consider a device with two network ports, where the task is to move data between the two connected networks while optionally performing some processing on the data. Examples include network infrastructure devices such as routers, firewalls, bridges, and protocol adapters; data sensing and remoting networks such as digital audio “snakes” and building/lighting/HVAC modules; production line process control systems; and countless others. Such devices transfer data between networks while analyzing, acting upon, and in some cases altering portions of the data to control upstream or downstream behavior.
In such multi-port devices, the majority of the data is transited verbatim from one port, through the device, to another port. Small percentages may be analyzed, and if warranted the same or other small sections may be altered by the device, but otherwise the bulk of the data is unchanged and passed along without requiring the attention of the device's host circuitry.
The key difference between single and multi-port devices is that their internal host circuitry is no longer the endpoint for network data. Any data being transited by the device from one port to another is, by definition, intended for other devices—and the throughput requirements of those other devices may far exceed those of the multi-port device's own host circuitry.
Unfortunately, this conflicts with the tidy relationship described above where the throughput requirements of the device's host circuitry define the throughput requirements of the device as a whole. In a multi-port device, the effects of its throughput limitations are not limited to itself; they are also imposed upon the connected networks and all other devices connected to them.
Returning to our two port device example: if it has two 100 Mbps ports but can only transit data at a maximum of 5 Mbps due to cost-efficient but slow internal host circuitry, that 5 Mbps limitation will be imposed upon all data passing between the two networks. Its network interface IC's may well be capable of handling the full 100 Mbps, but the host circuitry between those two interface IC's simply cannot sustain the throughput. The two-port device is thus a severe bottleneck in an otherwise high-speed environment. The classic example of a soda straw connecting two firehoses is particularly illustrative.
Earlier attempts to solve this problem have met with mixed results. Some prior art simply increases the host circuitry's capacity such that it can sustain the full network bandwidth. Essentially, the entire system is made fast enough by brute force. Doing so, however, dramatically increases the cost of the entire device for no benefit other than network throughput.
Another approach seen in prior art adds dedicated, high-speed Direct Memory Access (DMA) circuitry to the host to handle the transfer of data to and from the network interface IC's. This permits the original, simpler host circuitry to remain relatively unmodified. However, to support high-speed data movement between the network interface IC's there must be high-speed data buses and their attendant support devices, which add cost and design complexity to the host circuitry. The additional DMA hardware further increases cost, complexity, power consumption, and heat dissipation. The memory itself must be made fast enough to sustain the data rate, and in some cases expensive and complicated dual-port memories must be used. The original host circuitry must also be able to interface to the high-speed data buses and faster memory, leading to even greater cost increases and once again altering the design goals of the device.
It is clear that the need exists for high-speed network support on multi-port devices while maintaining minimal cost and complexity. Multi-port networked devices are manufactured and sold by the tens of millions annually worldwide. Cost-to-build is exceptionally important. Other considerations such as power consumption and heat dissipation also warrant concern as energy costs and environmental impacts become ever more significant. Small increases or reductions in per-device cost, power, and heat can have extraordinary multiplicative effects. An invention that enables high-speed networking while lowering cost, complexity, power, and heat would be extraordinarily important and valuable.